1. Field of the Invention
The present invention relates to a semiconductor memory device and a control circuit therefor, and more particularly, it relates to a structure for efficiently accessing a semiconductor memory device in a circuit device including a processor and the semiconductor memory device which are integrated on a common semiconductor chip (substrate).
2. Description of the Background Art
FIG. 40 schematically illustrates the structure of a conventional microprocessor having a built-in main memory. Referring to FIG. 40, a DRAM (dynamic random access memory) serving as a main memory and a CPU (central processing unit) serving as a processor are integrated on a common semiconductor chip in the conventional microprocessor. This microprocessor further includes an SRAM (static random access memory) cache SCH for storing data/instructions relatively frequently accessed by the CPU for efficiently transferring data between the DRAM and the CPU, a data queue DTQ for queuing and storing the data used by the CPU, an instruction queue ITQ for queuing and storing the instructions executed by the CPU, a tag memory TGM for storing addresses of the data stored in the SRAM cache SCH, and a memory controller MCL for referring to the tag memory TGM in accordance with access requests from the CPU, determining whether or not required data/instructions are stored in the SRAM cache SCH and performing necessary control in accordance with the result of the determination.
The memory controller MCL controls data read/write operations of the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH, while controlling reading/writing of data/instructions from/in the DRAM. The DRAM, the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH are interconnected with each other by a data bus DBS. The memory controller MCL transmits commands for instructing necessary operations to the DRAM through a DRAM control bus CBS, and outputs addresses specifying accessed memory positions of the DRAM through a DRAM address bus ABS. The operation is now briefly described.
In accordance with an access request from the CPU, the memory controller MCL refers to the tag memory TGM in accordance with an address signal supplied together with this access request, and determines whether or not data access-requested by the CPU is present in the SRAM cache SCH. The tag memory TGM stores respective addresses (cache block (set) addresses) of a plurality of cache blocks stored in the SRAM cache SCH in tag address positions. The memory controller MCL supplies the tag memory TGM with a cache block address (set address) and a tag address in the address signal received from the CPU. The tag memory TGM reads the corresponding cache block address (set address) in accordance with the supplied tag address, and determines whether or not the read set address matches that supplied from the memory controller MCL. If the set addresses match each other, the tag memory TGM asserts a signal CH indicating a cache hit. If these addresses mismatch each other, on the other hand, the cache hit signal CH from the tag memory TGM is negated.
The memory controller MCL controls necessary data transfer in accordance with the cache hit/miss indication signal CH supplied from the tag memory TGM. In case of a cache hit, the memory controller MCL transfers the instruction/data access-requested by the CPU to the instruction queue ITQ or the data queue DTQ from the SRAM cache SCH. Then, the instruction queue ITQ or the data queue DTA supplies the instruction or the data to the CPU. After this transfer, the memory controller MCL transfers the remaining instructions/data of the access-requested cache block to the instruction queue ITQ or the data queue DTQ from the SRAM cache SCH at need.
In case of a cache miss, on the other hand, the memory controller MCL informs the CPU of the cache miss in which no necessary instruction/data is supplied if no usable instruction/data is present in the queue ITQ or DTQ, and temporarily interrupts the operation of the CPU. The memory controller MCL accesses the DRAM through the DRAM control bus CBS and the DRAM address bus ABS, and transfers a cache block including the data access-requested by the CPU to the SRAM cache SCH through the data bus DBS. In this data transfer, the DRAM transfers an instruction/data to the instruction queue ITQ or the data queue DTQ. Whether what is transferred is instruction or data is determined by a bit supplied from the CPU to the memory controller MCL. If an instruction/data is present in the instruction queue ITQ or the data queue DTQ during the data transfer from the DRAM to the queue ITQ or DTQ and the SRAM cache SCH, the memory controller MCL allows the CPU to access the instruction queue ITQ or the data queue DTQ. A penalty for the cache miss is reduced by using the queue.
As hereinabove described, necessary data of cache blocks stored in the SRAM cache SCH are queued and stored in the instruction queue ITQ and the data queue DTQ respectively through the fact that localization is present in address positions accessed by the CPU (successive addresses are sequentially accessed in a single processing), whereby necessary data can be transferred to the CPU at a high speed.
Further, the DRAM and the CPU are integrated and formed on the common semiconductor chip, whereby the data can be transferred between the DRAM, the instruction queue ITQ, the data queue DTQ and the SRAM cache SCH at a high speed. Namely, the line capacitance of the internal data bus DBS which is provided on the semiconductor chip is so small that the data can be transferred at a higher speed as compared with a case of employing a discrete DRAM. While data transfer is limited by the number of data input/output pin terminals in case of employing a discrete DRAM, a large quantity of data/instructions can be simultaneously transferred by employing the internal data bus DBS having a large bit width, whereby high-speed data transfer is implemented.
FIG. 41 schematically illustrates the internal structure of the DRAM shown in FIG. 40.
Referring to FIG. 41, the DRAM includes a command latch 900 for latching a command supplied from the memory controller MCL through the DRAM control bus CBS in synchronization with a clock signal P1, an address latch 901 for latching an address signal supplied from the memory controller MCL through the DRAM address bus ABS in synchronization with the clock signal P1, a DRAM row controller 902 for decoding the command latched by the command latch 900 and generating a necessary control signal in accordance with the result of the decoding, a row address latch (row latch) 903 for latching an internal address signal Ad supplied from the address latch 901 in response to a row address latch instruction signal RAL from the DRAM controller 902, a row predecoder 904 for predecoding a row address signal RA from the row address latch 903 and outputting a row selection signal X, a DRAM column controller 906 for decoding the command from the command latch 900 and outputting a control signal related to column selection in accordance with the result of the decoding, a column address latch (column latch) 908 for latching the internal address signal Ad supplied from the address latch 901 in response to a column address latch instruction signal CAL from the DRAM column controller 906, a column predecoder 910 for predecoding an internal column address signal CA from the column address latch 908 and outputting a column selection signal Y, and a DRAM array 912 having dynamic memory cells arranged in a matrix.
This DRAM array 912 further includes a peripheral control circuit for sensing, amplifying and reading/writing data from/in a selected memory cell.
A row related control signal from the DRAM row controller 902 related to row selection is supplied to a row related control circuit included in the DRAM array 912, while a column related control signal from the DRAM column controller 906 is supplied to a column related control circuit included in the DRAM array 912 for performing an operation related to column selection.
The predecode signals X and Y from the row and column predecoders 904 and 910 are further decoded by row and column decoders (not shown) provided in the DRAM array 912 respectively, for selecting corresponding row and column respectively.
The DRAM shown in FIG. 41 incorporates a command and an address signal in synchronization with the clock signal P1, which in turn also determines a data output timing. The operation is now briefly described.
A control signal from the memory controller MCL (see FIG. 40) is outputted in the form of a command, and latched by the command latch 900 in synchronization with the clock signal P1. On the other hand, an address signal from the memory controller MCL is latched by the address latch 901 in synchronization with the clock signal P1.
A case is considered that the command instructs activation of row selection in the DRAM array 912, i.e., activation of a word line. The DRAM controller 902 decodes the row active command supplied from the command latch 900, activates the row address latch instruction signal RAL, and makes the row address latch 903 latch the address signal Ad supplied from the address latch 901. The internal row address signal RA latched by the row address latch 903 is predecoded by the row predecoder 904 (this activation timing is decided by the DRAM row controller 902), and supplied to the row decoder included in the DRAM array 912.
In the DRAM array 912, the row decoder (not shown) further decodes the predecoded signal X, and selects a corresponding row (word line). Thus, the DRAM array 912 is activated. Thereafter a sense amplifier (not shown) included in the DRAM array 912 senses and amplifies data of a memory cell on the selected row in accordance with the row related control signal from the DRAM row controller 902.
Another case is considered that the memory controller MCL supplies a read or write command instructing data reading or writing. In this case, the DRAM array 912 has already been activated to have a row (word line) selected, and memory cell data connected to the selected word line has been sensed and amplified and thereafter latched by the sense amplifier.
When the read or write command is supplied, the DRAM column controller 906 decodes this command, activates the column address latch instruction signal CAL, and makes the column address latch 908 latch the internal address signal Ad supplied from the address latch 901. Then, the column predecoder 910 predecodes the internal column address signal CA supplied from the column address latch 908, for supplying to the column decoder (not shown) included in the DRAM array 912.
This column decoder (not shown) decodes the column predecode signal Y, and selects the corresponding column of the DRAM array 912. The data is read from or written in the selected column through the data bus DBS. This data reading/writing is executed by a read or write circuit (not shown) included in the DRAM array 912 (this read/write circuit is controlled by the column related control signal).
The data reading/writing on the data bus DBS is executed in synchronization with the clock signal P1. Command and address signals are inputted and data is read/written in synchronization with the clock signal P1, whereby memory cell selection can be performed at a faster timing because of no necessity of considering a timing margin for a signal skew, and the access time is reduced in response. Further, the data is read/written in synchronization with the clock signal P1, whereby the data read/write speed is decided by the clock signal P1, resulting in high-speed data transfer.
Further case is considered that a copy operation is performed for transferring a data block Ds of a certain page of the DRAM array 912 to another page, as shown in FIG. 42A. The term "page" corresponds to a word line in the DRAM array 912. In other words, considered is an operation of transferring the data block Ds on a word line WLs onto another word line WLd, as shown in FIG. 42A. As to a main storage update algorithm, it is assumed that data which is written in the SRAM cache SCH is also written in the corresponding address position of the DRAM 912 (write through). Namely, no data block is transferred from the SRAM cache SCH to the DRAM 912 in a cache miss. This data block transfer operation is now described with reference to a timing chart shown in FIG. 42B.
A case is considered that the SRAM cache SCH stores another data block on the word line WLs. When the CPU makes an access request, this results in a cache miss since the data block Ds is not stored in the SRAM cache SCH. This is a "page hit" case, and the DRAM controller 902 generates a read command DRT. In accordance with this input command DRT, the column address latch instruction signal CAL supplied from the DRAM controller 906 is temporarily inactivated, and the column address latch 908 is released from a latch state and brought into a through state. Therefore, the column address latch 908 (see FIG. 41) outputs a column address signal CAs which is supplied simultaneously with the read command DRT. The column address latch 908 latches this column address signal CAs when the column address latch instruction signal CAL is activated again.
In accordance with the latched column address signal CAs, column selection is performed in accordance with the column predecoder 910 and the column decoder, so that the data block specified by the column address CAs on the selected word line WLs is read on a global I/O bus GIO which is an internal data bus of the DRAM array 912. An input/output circuit (not shown) of the DRAM array 912 reads in the data block Ds which is read on the global I/O bus GIO in synchronization with the clock signal P1, and outputs the same onto the data bus DBS. The read data block Ds is transferred to the data queue DTQ, and then stored in a general register in the CPU.
Then, the CPU outputs an access request again. This new access request specifies another page, and hence the memory controller MCL generates a precharge command PCG and supplies the same to the DRAM. In the DRAM, the DRAM array 912 is inactivated (the selected word line WLs is brought into a non-selected state) in accordance with the precharge command PCG under control by the DRAM row controller 902. Further, the respective circuits in the DRAM array 912 return to precharge states. In the following description, the wording "activation of the array" indicates such a state that a word line of the DRAM array 912 is driven to a selected state so that the sense amplifier latches memory cell data, and the wording "the array is inactivated" indicates such a state that each signal line of the array 912 returns to a prescribed precharge potential.
After a lapse of a clock cycle corresponding to a prescribed RAS precharge period tRP after supply of the precharge command PCG, a row related activation command (active command) ACT is generated and a destination row address (page address) is outputted. In accordance with the active command ACT, the DRAM row controller 902 temporarily inactivates the row address latch instruction signal RAL, and makes the row address latch 903 latch a row address signal RAd. Then, a corresponding page (word line) WLd is driven to a selected state in accordance with the incorporated row address signal RAd.
After a lapse of a clock cycle corresponding to a RAS-CAS delay time, the memory controller MCL generates a write command DWT and supplies the same to the DRAM. The DRAM temporarily inactivates the column address latch instruction signal CAL in accordance with the write command DWT, and incorporates a column address signal CAd supplied together with the write command DWT for performing column selection. Simultaneously with the write command DWT, the CPU transmits data (Dd) which has been stored in its general register onto the data bus DBS. The data on the data bus DBS is incorporated in the interior of the DRAM in accordance with the write command DWT, and transferred onto the DRAM global I/O bus GIO. Then, the data Dd is transferred from the global I/O bus GIO to a column CLd selected in accordance with the column address signal CAd, and written in a selected memory cell on the word line WLd.
As hereinabove described, the DRAM must be temporarily returned to a precharge state for a subsequent activation thereof if the bank number is one, data is transferred from a certain memory address position to another one for copying, and these memory address positions are frequently not present in the same page. Therefore, a precharge operation and page selection must be performed in the DRAM and the data cannot be transferred at a high speed, and hence the system performance is disadvantageously reduced.
Further, a precharge operation and word line selection (array activation) of the DRAM array 912 must be performed, and signal lines are charged/discharged in the DRAM array 912, and hence power consumption is disadvantageously increased. In case of a single-bank structure, further, only one page is selected in the DRAM, and the page hit rate cannot be increased.